Enable-IT 895 Series Manual de usuario descargar pdf (Pagina 9)

AN-895

Rev. 0 | Page 9 of 16

Master Transmit

In order to transmit a byte, the data must first be loaded into

the transmit FIFO. The address of the slave must be specified in

the I2C0ADR register. For a write of data, the write (

) bit in

the address register must be set to zero. Writing to the

I2C0ADR register automatically generates a start condition.

On the first clock of each byte transmitted, an I

C interrupt is

generated. Bit 2 and Bit 1 in I2C0MSTA are set, indicating that

the master has just transmitted a byte and that the FIFO is

underflow. This allows the user to add a byte to the FIFO.

If only one byte is in the FIFO when initiating the transfer, the

first I

C interrupt occurs on the first clock of the address

transmitted. If two bytes are in the FIFO, then the interrupt is

generated on the first clock of the first byte transmitted.

The transmission ends when the FIFO is empty. A stop

condition is automatically generated. This occurs 5.1 μs after

the last byte is transmitted.

A simple example of how this operates is shown in the

flowchart in

Figure 16.

//ENABLE I2C on GPIO P1.0 AND P1.1

GP1CON = 0x22;

//RETURN FROM ISR

VECTOR TO

INTERRUPT SERVICE ROUTINE

//SET UP I2C MASTER MODE, 100kHz

I2C0CFG = 0x82;

I2C0DIV = 0xCFCF;

//CHECK FOR T

INTERRUPT

if ((I2C0MSTA AND 0x4) == 0x4)

//PLACE DATA IN T

FIFO

I2C0MTX = DATA;

//SPECIFY INTERRUPT SERVICE ROUTINE

AND ENABLE MASTER I2C INTERRUPT

IRQ = MY_IRQ_FUNCTION;

IRQEN = 0x400;

//PLACE FIRST TWO BYTES IN T

FIFO

I2C0MTX = 0x11;

I2C0MTX = 0x22;

//SET UP ADDRESS WITH W BIT SET TO 0

I2C0ADR = 0xA0;

DATA?

Figure 16. Master Transmit Flowchart

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

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