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AN-895

Rev. 0 | Page 8 of 16

Transmit FIFO

To transmit data, the I2C0STX/I2C0MTX registers must be

loaded. Writing a byte to the Tx register is equivalent to writing

to Byte 1 of the FIFO (see

Figure 12).

• If Byte 0 is empty, the byte in Byte 1 gets pushed to Byte 0

automatically. This is described in the state machine (see

Figure 13). Note that the states are visible to the user in the

I2C0FSTA register.

• If Byte 0 is already full, the byte stays in Byte 1. Writing in

Tx again overwrites Byte 1.

Setting the transmit FIFO flush bit in the I2CFSTA register

empties the FIFO.

When a transmission occurs, Byte 0 is transmitted, Byte 1 is

shifted to Byte 0, and the FIFO is in State 2.

Receive FIFO

When receiving data, the data arrives in Byte 0.

• If Byte 1 is empty, Byte 0 is shifted automatically to Byte 1.

• If Byte 1 is already full, Byte 0 stays until I2C0SRX is read

(equivalent to reading Byte 1).

• If other data arrive while the FIFO is full, the slave delivers

a NACK for the data and Bit 4 of I2C0SSTA is set.

OUT

I2C0STX

BYTE 1 BYTE 0

Figure 12. Transmit FIFO

WRITE Tx

TRANSMIT

TRANSMIT/

Tx FIFO

FLUSH

Tx FIFO

FLUSH AUTOMATIC

STATE 0

FIFO EMPTY

STATE 1

BYTE 1 FULL

STATE 2

BYTE 0 FULL

STATE 3

FIFO FULL

Figure 13. Transmit FIFO State Machine

IC0SRX

BYTE 1 BYTE 0

Figure 14. Receive FIFO

RECEIVE

READ Rx

AUTOMATIC

STATE 0

FIFO EMPTY

STATE 1

BYTE 0 FULL

STATE 2

BYTE 1 FULL

STATE 3

FIFO FULL

Figure 15. Receive FIFO State Machine

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

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