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AN-895

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I2CxCFG: I

C Configuration Register

Table 3. I2CxCFG MMR Bit Descriptions

Bit No. Description

31 to 15 Reserved. These bits should be written by the user as 0.

14 Enable Stop Interrupt.

Set by the user to enable the generation of an interrupt on receiving a stop condition after receive a valid start + matching address.

Cleared by the user to disable the generation of an interrupt on receiving a stop condition.

13 to 12 Reserved. These bits should be written by the user as 0.

11 Enable Stretch SCL (Holds SCL Low).

Set by the user to enable stretching of the SCL line. This bit instructs the I

C interface to hold SCL low if it is already low, or

when it next goes low.

Cleared by the user to disable stretching of the SCL line.

10 Reserved. This bit should be written by the user as 0.

9 Slave Tx FIFO Request Interrupt Enable.

Set by the user to disable the slave Tx FIFO request interrupt.

Cleared by the user to generate an interrupt request just after the negative edge of the clock for the R/

W bit. This allows the

user to input data into the slave Tx FIFO if it is empty. At 400 kbps and the core clock running at 41.78 MHz, the user has 45

clock cycles to take appropriate action, taking interrupt latency into account.

8 General Call Status Bit Clear.

Set by the user to clear the general call status bits.

Cleared automatically by hardware after the general call status bits have been cleared.

7 Master Serial Clock Enable Bit.

Set by the user to enable generation of the serial clock in master mode.

Cleared by the user to disable serial clock in master mode.

6 Loop Back Enable Bit.

Set by the user to internally connect the transition to the reception, and to test user software.

Cleared by the user to operate in normal mode.

5 Start Back-Off Disable Bit.

Set by the user in multimaster mode. If losing arbitration the master tries to transmit again immediately.

Cleared by the user to enable start back-off. The master after losing arbitration waits before trying to transmit again.

4 Hardware General Call Enable.

When this bit and the general call enable bit are set, and have received a general call (Address 0x00) and a data byte, the

devices checks the contents of the I2C0ALT against the receive register. If they match, the device has received a hardware

general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to

turn to. The ADuC702x watch for these addresses. The device that requires attention embeds its own address into the

message. All masters listen and the master that knows how to handle the device contacts its slave and acts appropriately.

The LSB of the I2C0ALT register should always be written as a 1, as per the I

C-Bus Specification, version 2.1, January 2000.

3 General Call Enable Bit.

Set this bit to enable the slave device to deliver an ACK for an I

C general call, Address 0x00 (write). The device then

recognizes a data bit. If it receives a 0x06 as the data byte, that is, “reset and write programmable part of slave address by

hardware,” the I

C interface resets as per the I

C-Bus Specification. This command can be used to reset an entire I

C system.

The general call interrupt status bit sets on any general call. It is up to the user to take correct action by setting up the I

interface after a reset. If it receives a 0x04 as the data byte, that is, “write programmable part of slave address by hardware,”

the general call interrupt status bit sets on any general call. It is up to the user to take correct action by reprogramming the

device address.

2 Reserved.

1 Master Enable Bit.

Set by the user to enable the master I

C channel.

Cleared by the user to disable the master I

C channel.

0 Slave Enable Bit.

Set by the user to enable the slave I

C channel. A slave transfer sequence is monitored for the device address in I2C0ID0,

I2C0ID1, I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence.

Cleared by the user to disable the slave I

C channel.

1 2 ... 9 10 11 12 13 14 15 16

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