Enable-IT 895 Series Manual de usuario descargar pdf (Pagina 6)

AN-895

Rev. 0 | Page 6 of 16

Clock Stretching

In an I

C communication, the master device determines the

clock speed. Unlike RS232, the I

C bus provides an explicit

clock signal that relieves master and slave from synchronizing

exactly to a predefined baud rate.

However, there are situations where an I

C slave is not able to

cooperate with the clock speed given by the master and needs to

slow down a little. This is done by a mechanism referred to as

clock stretching.

An I

C slave is allowed to hold down the clock if it needs to

reduce the bus speed. The master, on the other hand, is required

to read back the clock signal after releasing it to a high state and

wait until the line has actually gone high.

Bit 11 of the I2CxCFG MMR allows clock stretching.

SERIAL EEPROM PROTOCOLS

The ATMEL AT24C series serial EEPROM supports five

commands:

• Random write

• Sequential write

• Current address read

• Random read

• Sequential read

These five commands are described in

Figure 7 through

Figure 11.

START

DEVICE

ADDRESS

WRITE

WORD ADDRESS DATA

STOP

SDA LINE

MSB

LSB

R/W

ACK

LSB

ACK

MSB

ACK

Figure 7. Random Write

START

DEVICE

ADDRESS

WRITE

WORD ADDRESS (n) DATA (n)

SDA LINE

MSB

R/W

ACK

LSB

ACK

MSB

ACK

DATA (n + 1)

ACK

DATA (n + x)

STOP

ACK

Figure 8. Sequential Write

START

DEVICE

ADDRESS

READ

STOP

DATA

SDA LINE

MSB

R/W

ACK

LSB

NO ACK

Figure 9. Current Read

START

DEVICE

ADDRESS

WRITE

WORD ADDRESS (n)

SDA LINE

MSB

LSB

R/W

ACK

LSB

ACK

MSB

START

STOP

DEVICE

ADDRESS

READ

MSB

ACK

LSB

NO ACK

DATA (n)

DUMMY WRITE

Figure 10. Random Read

READ

DEVICE

ADDRESS

SDA LINE

ACK

NO ACK

ACK

STOP

R/W

DATA (n + 2) DATA (n + x)DATA (n + 1)DATA (n)

Figure 11. Sequential Read

1 2 3 4 5 6 7 8 9 10 11 ... 15 16

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