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AN-895

Rev. 0 | Page 3 of 16

C INTERFACE OVERVIEW

C is a 2-wire serial communication system developed by

Philips that allows multiple masters and multiple slaves to be

connected via two wires (SCL and SDA). In an I

C interface,

there must be at least a single master and a single slave.

The SCL signal controls the data transfer between master and

slave. The SCL signal is always transmitted from the master to

the slave. The slave, however, does have the ability to pull this

line low if it is not ready for the next transmission to begin. This

is called clock stretching. One clock pulse must be generated for

each data bit transferred.

The SDA signal is used to transmit or receive data. The SDA

input must be stable during the high period of SCL. A transition

of the SDA line while SCL is high is seen as a start or stop

condition (see

Figure 2 and Figure 3).

C FUNDAMENTALS

Start Condition

A typical data transfer sequence for an I

C interface starts with

the start condition. The start condition is simply a high to low

transition in the SDA line while the SCL line is pulled high (see

Figure 2). The master is always responsible for generating the

start condition. The start (and stop) conditions are the only

times that the SDA line should change during a high period of

the SCL line. During normal data transfer (including slave

addressing), the data on the SDA line must be stable during the

high period of the SCL line.

06549-002

SCL

SDA

START

Figure 2. Start Condition for I

06549-022

SCL

SDA

STOP

Figure 3. Stop Condition for I

Slave Address

After the start condition, the master sends a byte, most

significant bit (MSB) first, on the SDA line, along with eight

SCL pulses. The first seven bits of this byte is the 7-bit slave

address. The slave only responds to the master if this 7-bit

address matches the address of the slave device (or one of the

four slave addresses). The eighth bit, the least significant bit

(LSB), is the R/

status bit. The R/

status bit determines the

direction of the message. If this bit is cleared, the master writes

data to a selected slave. If this bit is set, the master expects to

receive data from the slave. The master generates the clock in

both cases.

If the slave receives the correct address, that is, the seven MSBs

from the master match the seven MSBs of the I2C0ADR

memory mapped register (MMR), the slave returns a valid

ACK, pulls the SCL line low, and sets flags in the I2C0STA.

While the slave does all the manipulation of the I

C slave

addressing automatically in hardware, as described previously, it

is up to the master to output the slave address appropriately.

Acknowledge (ACK)/No Acknowledge (NACK)

If the slave address matches the address sent by the master, the

slave automatically sends an acknowledge (ACK). Otherwise, it

sends a no acknowledge (NACK). An ACK is seen as a low level

on the SDA line on the ninth clock pulse. A NACK is seen as a

high level on the SDA line on the ninth clock pulse (see

Figure 4).

During data transfer, the ACK or the NACK is always generated

by the receiver. However, the clock pulse required for the ACK

is always generated by the master. The transmitter must release

the SDA line (high) during the ACK clock pulse. For a valid

ACK, the receiver must pull the SDA line low.

On the ADuC702x MicroConverter, both the ACK and the

NACK are automatically generated in hardware, at the end of

each byte in the reception.

If a master receives a NACK from a slave-receiver (either the

slave did not respond to the slave address or the data

transmitted), the master should generate the stop condition to

abort the transfer (see the

Data Transfer section).

A master receiver must signal the end of a data sequence to the

slave-transmitter by generating a no acknowledge (NACK) after

the last byte that was sent by the slave. Once the slave receives

the NACK, it releases the SDA line to allow the master to

generate the stop condition.

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