Enable-IT 895 Series Manual de usuario descargar pdf (Pagina 11)

AN-895

Rev. 0 | Page 11 of 16

Master Receive

In master mode, to read data from a slave, a similar approach is

used. First, the number of bytes to be read is configured by the

I2C0CNT register. This denotes the number of bytes to be read

from the slave, plus one. It can have a value between 0 and 7 but

can be reset during code execution in order to read larger

amounts of data.

In order to start receiving data, the read (R) bit is set in the

I2C0ADR register. This initiates a transfer with a start condition

generated with the address and a R/

bit set by the I2C0ADR

or NACK), an interrupt is generated. Bit 3 of I2C0MSTA is set,

indicating that a byte has just been received. Only reading

I2C0MRX clears this bit.

When the master does not need to receive more data, it

automatically generates a NACK to the last byte received. This

tells the slave to cease transmitting bytes and allows the master

to then generate a stop condition.

If the data received is not read on time and the FIFO is full, the

master delivers a NACK for the extra data received.

A flowchart of receiving four bytes from the slave is shown in

Figure 19.

The I2C0CNT is a load register to an internal counter that is

not user accessible. It is only a 3-bit counter, which means that

the master can only be configured to transmit eight bytes at a

time. However, it is possible to reload the internal counter by

writing in I2C0ADR during a transmit sequence.

//ENABLE I2C on GPIO P1.0 AND P1.1

GP1CON = 0x22;

VECTOR TO

INTERRUPT SERVICE ROUTINE

//SET UP I2C MASTER MODE, 100kHz

I20CFG = 0x82;

I20DIV = 0xCFCF;

//CHECK FOR R

INTERRUPT

if ((I2COMSTA AND 0x8) == 0x8)

//READ DATA FROM FIFO

dat[i] = I2C0MRX

//SPECIFY INTERRUPT SERVICE ROUTINE

AND ENABLE MASTER I2C INTERRUPT

IRQ = MY_IRQ_FUNCTION;

IRQEN = 0x400;

//SET NUMBER OF BYTES TO BE RECEIVED

I2C0CNT = 0x04;

//SET UP ADDRESS WITH R BIT SET TO 1

I2C0ADR = 0xA1;

//WAIT FOR FIRST BYTE TO BE RECEIVED

//RETURN FROM ISR

Figure 19. Master Receive Flowchart

1 2 ... 6 7 8 9 10 11 12 13 14 15 16

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