search

Enable-IT 895 Series Manual de usuario Pagina 4

  • Descarga
  • Añadir a mis manuales
  • Imprimir
  • Pagina
    / 16
  • Tabla de contenidos
  • MARCADORES
    • Valorado. / 5. Basado en revisión del cliente
Vista de pagina 3
AN-895
Rev. 0 | Page 4 of 16
Data Transfer
In the I
2
C interrupt service routine (ISR), or in a polled
implementation, the slave decides whether or not to transmit or
receive depending on the status of the R/
W
bit sent by the
master. The slave then either transmits or receives a bit on each
clock sent by the master. It is up to the master to provide the
nine clocks (eight for the data and one for the ACK) for the
slave to transmit/receive data to/from the master. The I
2
C
interrupt bit is set every time a valid data byte is transmitted or
received by the slave.
Note again that in a slave-transmitter, master-receiver system
the master must signal the end of a data sequence to the slave by
sending a NACK after the last byte transmitted by the slave.
Once the slave receives the NACK, it releases the SDA line to
allow the master to generate the stop condition.
If a master wants to abort a data transfer or to interrupt the data
transfer of another master on the bus, it can do this by sending
a start condition followed by a stop condition.
Stop Condition
The data transfer sequence is terminated by the stop condition.
A stop condition is defined by a low to high transition on the
SDA line while SCL is high (see
Figure 3).
The stop condition is always generated by the master. The
master sends the stop condition once the master is satisfied that
the data sequence is over or if it receives a NACK from the slave
device. The reception of the stop condition resets the slave
device into waiting for the slave address again.
The I
2
C interface on the ADuC702x parts can be configured to
generate an interrupt on the stop condition. This is enabled by
Bit 14 in the I2CxCFG MMR.
A typical transfer sequence is shown in
Figure 5.
0
6
5
4
9
-
0
0
3
S
D
A
F
L
O
A
T
S
(
H
I
G
H
)
F
O
R
N
A
C
K
R
E
C
E
I
V
E
R
P
U
L
L
S
S
D
A
L
O
W
F
O
R
A
C
K
T
R
A
N
S
M
I
T
T
E
R
R
E
L
E
A
S
E
S
S
D
A
C
L
O
C
K
P
U
L
S
E
F
O
R
A
C
K
N
O
W
LE
D
G
E
7
8
9
D
A
T
A
O
U
T
P
U
T
B
Y
R
E
C
E
I
V
E
R
D
A
T
A
O
U
T
P
U
T
B
Y
T
R
A
N
S
M
I
T
T
E
R
D
A
T
A
L
S
B
M
A
S
T
E
R
C
L
O
C
K
Figure 4. Acknowledge (ACK) and No Acknowledge (NACK) on the I
2
C Bus
0
6
5
4
9
-
0
0
4
MSB
START
BIT
SCL
ACK
BIT
ACK
BIT
STOP
BIT
SLAVE ADDRESS
SDA
MSBLSB LSB
DATA
1 178 8992
3 TO 6 2 TO 7
R/W
Figure 5. Typical I
2
C Transfer Sequence
Vista de pagina 3
1 2 3 4 5 6 7 8 9 ... 15 16

Comentarios a estos manuales

Sin comentarios
Relacionado con productos y manuales para No Enable-IT 895 Series
No Enable-IT 860 Series Manual de usuario   (14 paginas)
No Enable-IT 860C Manual de usuario   (5 paginas)
No Enable-IT 8424 Manual de usuario   (31 paginas)
  • Pro-Ject Amabilia Aquanami CTC Store Vox Technologies
  • Edelbrock Carros Genie Abridor De Puerta De Garage Sony Ericsson Las radios Baby Trend Cochecitos Epson Computadoras móviles de mano
  • Honda FG400 LG ND1520 Alphasonik PMA1200DE Acer B1-860A Bosch DWT069750
  • JL Audio XR650-CXi Manual de usuario LG DK172 Manual de usuario Art Pro Tube MP Especificaciones Sony BDV-E690 Manual de usuario Samsung GT-S7350/I Manual de usuario