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AN-895

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I2CxSSTA: Slave Status Register

Note: reading the status register modifies its contents. Only read it once and save its value in a variable during an ISR.

Table 4. I2CxSSTA MMR Bit Descriptions

Bit No. Description

31 to 15 Reserved. These bits should be written by the user as 0.

14 Start Decode Bit.

Set by the hardware if the device receives a valid start + matching address.

Cleared either by an I

C stop condition, or by an I

C general call reset.

13 Repeated Start Decode Bit.

Set by the hardware if the device receives a valid repeated start + matching address.

Cleared by either an I

C stop condition, by a read of the I2CxSSTA register, or by an I

C general call reset.

12 to 11 ID Decode Bit.

00 Received address matched ID Register 0

01 Received address matched ID Register 1

10 Received address matched ID Register 2

11 Received address matched ID Register 3

10 Stop After Start and Matching Address Interrupt.

Set by hardware if the slave device receives an I

C stop condition after a previous I

C start condition and matching address.

Cleared by a read of the I2CxSSTA register.

9 to 8 General Call ID.

00 No general call

01 General call reset and program address

10 General call program address

11 General call matching alternative ID

7 General Call Interrupt.

6 Slave Busy.

Set automatically if the slave is busy.

Cleared automatically.

5 No ACK.

Set if the master asks for data and no data is available.

Cleared automatically.

4 Slave Receive FIFO Overflow.

Set automatically if the slave receive FIFO is overflowing.

Cleared automatically by reading I2C0SRX.

3 Slave Receive IRQ.

Set after receiving data.

Cleared automatically by reading the I2C0SRX register.

2 Slave Transmit IRQ.

Set at the end of a transmission.

Cleared automatically by writing to the I2C0STX register.

1 Slave Transmit FIFO Underflow.

Set automatically if the slave transmit FIFO is underflowing.

Cleared automatically by writing to the I2C0STX register.

0 Slave Transmit FIFO Empty.

Set automatically if the slave transmit FIFO is empty.

Cleared automatically by writing to the I2C0STX register.

1 2 ... 10 11 12 13 14 15 16

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