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Hytec Electronics Ltd 8424TR/UTM/G/8/2.0

Page 8

4. Memory Map

A bit in the control register of the 8424 allows selection of either 1Mb memory (128K samples/channel)

when set at logic 1 or 2Mb (256K samples/channel) when set at logic 0.

The memory is divided into 4 segments allocated to conversions from ADC1 to ADC4 as shown in the

table below.

The Half Full flag is set when the number of conversion written to memory reaches 128k. The Full Flag

is set when 256K conversion have been logged in to memory.

1M = ‘0’ (bit 7 of the CSR) this sets memory size to 2Mb

Conversion Memory

ADC4 conversions 1 -256k

ADC3 conversions 1 -256k

ADC2 conversions 1 -256k

ADC1 conversion 256k

ADC1 conversion 256k-1

ADC1 conversion 2

ADC1 conversion 1

When 1Mb memory size set the channels are arranged as shown in the table below.

The Half Full flag is set when the number of conversion written to memory reaches 64k. The Full Flag is

set when 128K conversion have been logged in to memory.

1M = ‘1’ (bit 7 of the CSR) this sets memory size to 1Mb

Conversion Memory

Unused memory (512k)

ADC4 conversions 1 -128k

ADC3 conversions 1 -128k

ADC2 conversions 1 -128k

ADC1 conversion 128k

ADC1 conversion 128k-1

ADC1 conversion 2

ADC1 conversion 1

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 30 31

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