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Enable-IT 8424 Manual de usuario Pagina 18

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Hytec Electronics Ltd 8424TR/UTM/G/18/2.0
Page 18
7.3 Upper And Lower Threshold
The 16 bit Upper and Lower Threshold registers is loaded with the required values prior to digitisation.
During data acquisition the module compares the digitised data of the selected channel with the 16 bit
values loaded in the Upper and Lower Threshold register. When the data exceeds the pre-set value of the
Lower Threshold register the current contents of the Conversion Pointer register (CPR) is store in the
Lower Threshold Time Stamp register. Subsequently when the data falls below the Upper Threshold
register the current contents of the CPR is store in the Upper Threshold Time Stamp register.
If the input goes past LTH then address logged then after peak val reached will log UTH when reached.
If the input rise again and has a higher peak value than the first pulse the UTH will be cleared and a new
value will be logged when the input reaches the UTH value.
The following formula should be used to calculate the value loaded to the Upper or Lower Threshold
register:
( )
80000
0/Vrange
voltageThreshold
= alueregister v Threshold x
xFFFF
+
Where Vrange = 20 for +/-10V range and 10 for +/-5v range
7.3.1 Lower Threshold Registers
Read/write Address: Chan 1=2Chex, Chan 2=3Ahex, Chan 3=48hex, Chan 4=56hex.
When the data exceeds the pre-set value of the Lower Threshold register the current contents of the
Conversion Pointer Register (CPR) is store in the Lower Threshold Time Stamp register. Subsequently
when the data falls below the Upper Threshold register the current contents of the CPR is store in the
Upper Threshold Time Stamp register.
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
LTH15
LTH14
LTH13
LTH12
LTH11
LTH10
LTH9
LTH8
LTH7
LTH6
LTH5
LTH4
LTH3
LTH2
LTH1
LTH0
7.3.2 Upper Threshold Registers
Read/write Address: Chan 1=2Ehex, Chan 2=3Chex, Chan 3=4Ahex, Chan 4=58hex.
When the data falls below the Upper Threshold register the current contents of the CPR is store in the
Upper Threshold Time Stamp register.
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
UTH15
UTH14
UTH13
UTH12
UTH11
UTH10
UTH9
UTH8
UTH7
UTH6
UTH5
UTH4
UTH3
UTH2
UTH1
UTH0
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